1. Field of the Invention
This invention relates generally to semiconductor memory units implemented in integrated circuit technology and, more particularly, to the generation of delayed clock pulses in each memory unit which synchronize the operation of the stages of the memory unit.
2. Description of the Related Art
In semiconductor memory units implemented in integrated circuit technology, the operation of the memory unit stages is typically initiated with a signal, such as a RAS (row address signal) signal or a clock signal, generated by the associated central processing unit. In order to synchronize the operation of the memory stages, the initiating signal is used to generate delayed activation signals which control the operation of the individual stages of the memory unit.
Referring to FIG. 1a, the signal delay circuit 10 which, in the prior art, is used to generate a delay signal having a predetermined delay time, is shown. A input signal, SIGNAL IN, is applied to a gate terminal of n-channel field-effect transistor 11 and to a gate terminal of p-channel field-effect transistor 12. The source terminal of transistor 12 is coupled to the V.sub.DD voltage supply terminal, while the source terminal of transistor 11 is coupled to the ground potential. The drain terminal of transistor 12 is coupled to the drain terminal of transistor 11, to a first terminal of capacitor 13, and to an input terminal of inverting amplifier 14. The second terminal of capacitor 13 is coupled to the ground potential, while the output terminal of inverting amplifier 14 is the output signal, SIGNAL OUT, of the delay circuit.
Referring to FIG. 1b, a comparison of an idealized input signal, SIGNAL IN, and an idealized output signal, SIGNAL OUT, of the delay circuit 10 is shown. The input signal has a negative-going step at a given time t.sub.o. The output signal provides a negative-going step delayed by a time, D, with respect to the negative-going step of the input signal. The time delay, D, is a function of the size of capacitor C and the parameters of the semiconductor components. To provide an activation signal with a given time delay, the processing steps in fabricating the delay circuit have, in the past, been adjusted to provide the proper parameters which result in the desired time delay. The adjustments have included alteration of the masks used in fabricating the component. The changing of processing steps is time consuming and expensive.
To eliminate the need to adjust the fabrication of the components of the semiconductor chip to provide a delay circuit with the correct parameters, FIG. 2 shows a configuration wherein a plurality of delay circuits 10' through 10"' are coupled in series. Each delay circuit is provided with switches, 21' through 21"' and 22' through 22"'. The switches 21' through 21"' and 22' through 22"' can be placed in an open or closed position. The state of the switches 21' through 21"' and 22' through 22"' determine which of the delay circuits 10' through 10"' are electrically coupled in a series connection. By appropriate selection of the parameters of the individual delay circuits 10' through 10"' and the selection of the particular delay circuits 10' through 10"' coupled in series between the SIGNAL IN terminal and the SIGNAL OUT terminal, the delay of SIGNAL OUT signal can be controlled during the fabrication by the removal of conducting paths. When the delay time D is not satisfactory, a relatively simple change in the fabrication process, i.e. setting the state of the switches 21' through 21"' and 22' through 22"', can provide a controlled change in the delay time D. Although the setting of the switches in the fabrication process, or in the case of setting of the switches through post fabrication processes such as with laser techniques, provides an improvement over the adjustment of parameters of an individual delay circuit, further improvement in the ability to control the delay time D is desirable.
A need has therefore been felt for an apparatus and an associated method to provide a time delay apparatus which can be controlled without changing of the process steps. It would be further desirable to provide a time delay D of an output signal with respect to an input signal which can be controllable adjusted after fabrication by internally generated signals. It would be also desirable to control the delay time D of the delay circuit output signal by externally applied signals.